1. Technical Field
The present invention described herein generally relates to a semiconductor memory apparatus, and more particularly, to a control circuit of a read operation for a semiconductor memory apparatus.
2. Related Art
Typical semiconductor memory apparatuses use a parallel input/output system for exchanging data with an external chipset using a single port having a plurality of input/output pins. The parallel input/output has an advantage of processing data at a high speed since the parallel input/output can simultaneously transmit several bits of data.
However, the parallel input/output has a disadvantage in that the number of buses required for transmitting data increases and the more the data transmission distance increases, which results in an increased unit cost of the product.
A SERDES (SERializer and DESeriallizer) has been used in the conventional art in order to supplement the disadvantages of the parallel input/output. In the SERDES, a semiconductor memory apparatus is provided with two or more ports with each port including a SERDES circuit. Each of the ports converts series signals that are externally inputted into parallel signals and transmits them to a memory bank, and also converts parallel signals that are inputted from the memory bank into series signals and outputs them to the outside.
According to these operations, a SERDES type memory apparatus can reduce the number of bus lines required.
In the SERDES, at least two write/read operations are executed for every one write/read command. Accordingly, in a SERDES type semiconductor memory apparatus having a CAS-to-CAS is delay ‘tCCD’ of four clocks, one write/read operation should be executed within two clocks.
Presently, the time interval for this operation is fixed. Accordingly, one time period for a write/read operation should be executed within 2 ns for a target frequency of 1 ns. That is, a column selection signal ‘YI’ for controlling the first write/read operation and a column selection signal ‘YI’ for controlling the second write/read operation should not be delayed by more than 2 ns.
In addition, the time interval between the two column selection signals ‘YI’s is a fixed value corresponding to a high-frequency operation, without consideration to the operational speed of the semiconductor memory apparatus. Accordingly, the semiconductor memory apparatus always operates with the predetermined minimum margin.
FIG. 1A and FIG. 1B are circuit diagrams showing a procedure for a command process in a conventional SERDES semiconductor memory apparatus.
First, FIG. 1A is a circuit diagram showing a write operation.
First, a write command ‘WT’ that is created by a command decoder (not shown) is enabled and supplied to a column decoder 101. The column decoder 101 receives an address signal ‘ADD’ and the write command ‘WT’ and creates a first column selection signal ‘YI1’ and a second column selection signal ‘YI2’ synchronized with a clock signal ‘CLK’ supplied to the column decoder 101. The second column selection signal ‘YI2’ can be a signal that is delayed by a predetermined time interval, e.g., two periods of the clock signal, and in synchronization with the first column selection signal ‘YI1’.
Further, data input multiplexers ‘MUX1’, ‘MUX2’ 103, 105 each receive the column selection signals ‘YI1’, ‘YI2’ and data ‘DIN’ such that the data can be transmitted to a memory bank. According to this configuration, the input data ‘DIN’ is inputted to a port after undergoing a predetermined process according to a data strobe signal ‘DQS’ from a data input pad ‘DQ’ and is parallelized. Then, the input data ‘DIN’ is transmitted to the data input multiplexers 103, 105 through a global input/output line ‘GIO’.
A write driver 107 transmits the data received from the input multiplexers ‘MUX1’ and ‘MUX2’, which receive the input data through the global input/output line, to a memory bank block through a local input/output line ‘LIO/LIOb’.
For example, when two write operations are executed for one write command, input data having 8 bits is parallelized to 4 bits-by-4 bits and sequentially inputted through the GIO to the input multiplexers ‘MUX1’ and ‘MUX2’. Further, the data input multiplexer ‘MUX1’ 103 transmits the first 4 bits of data to the local input/output line ‘LIO/LIOb’ via the write driver 107 according to the first column selection signal ‘YI1’. Thereafter, the data input multiplexer ‘MUX2’ 105 transmits the second 4 bits of data to the local input/output line ‘LIO/LIOb’ via the write driver 107 according to the second column selection signal ‘YI2’ that is outputted after a predetermined time interval (i.e., two clocks).
As described above, it is possible to transmit the data inputted according to the data strobe signal to the memory bank at an exact time since the column selection signals ‘YI1’ and ‘Y12’ are created in synchronization with the clock signals during the write operation.
Next, FIG. 1B is a circuit diagram showing a read operation.
As a read command ‘RD’ is enabled, a column decoder 201 receives an address signal ‘ADD’ and the read command ‘RD’ and outputs a column selection signal ‘YI’. Accordingly, an input/output sense amplifier 205 receives data ‘DOUT’ stored in the memory bank block through the local input/output line ‘LIO/LIOb’ and subsequently amplifies and latches the data.
In response to an output signal of a first delay unit 215, the data amplified by the input/output sense amplifier 205 is transmitted to a pipe latch 213 through global input/output line drivers 207, 209 and a multiplexer 211. In this configuration, the first delay unit 215 delays a sensing-enable signal ‘IOSTB’ outputted from a sensing-enable signal generator 203 for a predetermined amount of time and then outputs it.
More specifically, a portion (a first data group) of the output signals from the input/output sense amplifier 205 is transmitted to the multiplexer 211 through a global input/output driver according to a first delay signal ‘MAO<1>’ outputted from the first delay unit 215. The rest (a second data group) of the output signals from the input/output sense amplifier 205 are then transmitted to the multiplexer 211 through a global input/output driver according to a second delay signal ‘MAO<2>’ outputted from the first delay unit 215. According to this configuration, the second delay signal ‘MAO<2>’ is a value obtained by delaying the first delay signal ‘MAO<1>’ by a predetermined time.
The first data group is inputted to the multiplexer 211 and should be stored in the pipe latch 213 before the second data group is inputted to the multiplexer 211. Therefore, first and second pipe latch control signals ‘PIN1’, ‘PIN2’ that are created by a second delay unit 217 should be designed so as to have the same delay values as the first and second delay signals ‘MAO<1>’, ‘MAO<2>’ that are outputted from the first delay unit 215, respectively.
As described above, the first delay unit 215 and the second delay unit 217 are designed to have a fixed delay time, regardless of the operational speed of a semiconductor memory apparatus. However, the positions of the first delay unit 215 and the second delay unit 217 are designed differently and therefore, there is difficulty in configuring the delay units 215, 217 to have the exact same delay values. As a result, a problem occurs where the data that has been transmitted to the global input/output line is not transmitted to the pipe latch 213 at the exact time. This problem can be exacerbated in a high-frequency operation and cause the semiconductor memory apparatus to malfunction.
Further, since the delay times applied to the first delay unit 215 and the second delay unit 217 are values created by fixing the sensing-enable signal ‘IOSTB’ for a predetermined time, the first delay unit 215 and the second delay unit 217 operate according to the fixed value, even though the operational margin is sufficient in a low-frequency operation, such that the efficiency of the semiconductor memory apparatus is deteriorated.